Heretofore, it has been necessary to trade DC power consumption for speed and/or drive capability in TTL to CMOS logic level translator design. For example, consider the prior-art-type CMOS inverter illustrated in FIG. 1 of the drawing generally designated by the numbers 10. Inverter 10 is shown to include a P-channel, field-effect transistor (FET), which is designated 12, and an N-channel, field-effect transistor, designated 14. Transistors 12 and 14 are connected in what is referred to herein as a (P-channel over N-channel) totem-pole configuration. More specifically, transistor 12 is configured in a CMOS, pull-up configuration, with the transistor gate connected to a (data) input line 20, with the (end of the channel referred to herein as the) transistor source connected to receive a DC power supply potential (Vcc), and with the (other end of the channel, referred to herein as the) transistor drain connected to a (data) output line 22, upon which inverter 10 develops a data output signal. Transistor 14 is configured in a CMOS, pull-down configuration, with the transistor gate connected to line 20, with the transistor drain connected to line 22, and with the transistor source connected to receive a circuit ground potential (Vss).
Operationally, when a low logic signal level potential is externally developed on line 20, transistor 12 is turned on; and, transistor 14 is turned off. With transistor 12 on and transistor 14 off, transistor 12 sources a current flow from the power supply potential (Vcc) into line 22, developing a high, CMOS, logic signal level potential on the line. When a high, CMOS, logic signal level potential is externally developed on line 20, transistor 12 is turned off; and, transistor 14 is turned on. With transistor 12 off and transistor 14 on, transistor 14 sinks a current flow from line 22 to circuit ground (Vss), developing a low, CMOS, logic signal level potential on the line. When a high, TTL, logic signal level potential (a potential of at least 2.4 volts) is externally developed on line 20, transistor 14 is turned on. However, the high, TTL, logic signal level potential may not be high enough to turn transistor 12 off. As a consequence, a (DC power consuming) steady-state (quiescent) current may flow from the power supply potential (Vcc) through transistors 12 and 14 to circuit ground (Vss). The level of the quiescent current flow is dependent upon the width of the channels of transistors 12 and 14. If transistors 12 and 14 have relative narrow channels, the quiescent current level will be relatively low. However, with relatively narrow channels, the transistors will have a relatively low drive capability.
To both reduce the level of the quiescent current flow and maintain relatively high drive capability, the prior-art-type TTL to CMOS logic level translator illustrated in FIG. 2 of the drawing, generally designated by the numbers 30, may be used. Translator 30 is shown to employ three inverters connected in cascade. More specifically, translator 30 includes a pair of transistors 40 and 42 connected (in the P-channel over N-channel totem-pole configuration) as an inverter between a (data input) line 44 and a line 46; another pair of transistors 50 and 52 connected (in the P-channel over N-channel totem-pole configuration) as an inverter between line 46 and a line 56; and, yet another pair of transistors 60 and 62 connected (in the P-channel over N-channel totem-pole configuration) as an inverter between line 56 and a (data output}line 66. To minimize the level of the (DC power consuming) quiescent current flow, transistors 40 and 42 have relatively narrow channels. To maximize drive capability, transistors 60 and 62 have relatively wide channels. Unfortunately, however, because of the three inverters, each contributing one gate delay, translator 30 is relatively slow.